The use of mass storage devices in computer systems and, particularly, methods and systems for utilizing cache memory subsystems of mass storage devices are well known. It is also well known to use a memory subsystem as a cache memory to improve the performance of a mass storage system.
A cache storage system can form part of a mainframe computer system, a computer workstation, or any other data processing system in which one or more of processes utilize system resources including cache memory. In a computer system, a cache memory is typically placed between a processor and a larger but slower memory device, for example, a direct access storage device (DASD). Cache memory is used to store data read from the slower memory device which contains the referenced data segment. Storing frequently referenced data segments in cache memory decreases average reference time because of the speed advantage of cache memory over main storage. When the cache memory is filled, older, less recently accessed data is discarded to make room for newer, more recently referenced data. In caching operations, the fundamental caching problem involves establishing an efficient scheme for maximizing the rate of successful data references. Ideally, data is consistently found in cache memory whenever it is referenced.
When data referenced by a process is found in cache memory, the reference is deemed successful and is called a "hit". Conversely, when referenced data is not found in cache memory, the reference is called a "miss". The referenced data not found in cache memory is typically transferred to the cache memory in order to increase the probability of future hit references. When the referenced data is located in cache memory, it replaces data already in cache memory. The deallocated data, typically, the least recently referenced data, is discarded from the bottom of the cache memory.
In order to improve caching efficiency, cache memory management techniques use hit/miss ratio to dynamically control cache memory space and time allocation. Some conventional techniques for allocating cache memory, dynamically evaluate hit rate performance utilizing a process or an algorithm to determine what portion of the cache memory needs to be assigned to each cache memory user. In contrast, other conventional techniques use an arrangement for varying the size of allocated buffers as a function of hit/miss ratio. But, because substantial memory overhead is needed, concerns related to proper utilization of the cache memory arise when such techniques are employed. On one hand, cache memory is regarded as a finite resource. On the other hand, caching operations efficiency is linked to sufficient cache memory allocation.
For example, in systems that utilize write-back caching, write operations will be deferred until destaging is performed thereby adversely affecting caching operations efficiency, unless adequate memory space is available for the write operations. Accordingly, techniques that allocate too much or too little cache memory are deficient. Thus, some conventional methods and systems regulate caching operations in an attempt to more usefully allocate cache memory and speed up data transfer rates. When the resultant caching operations are made more efficient, access delay components are eliminated from the host CPU response time.
However, a problem frequently encountered is how much data to store in cache memory to increase computer system operations efficiency. In a cache disk controller, the amount of data to cache when referenced data not found in cache memory produces a cache miss is a significant determiner of performance. A method and a system for determining the optimal portion of data to be stored result in optimal caching operation and, in turn, in efficient computer operations.
Choosing the wrong mode of caching, that is, the wrong amount of data to cache, results in performance penalties. Staging too much data uses excessive disk and back end data path resources making them unavailable for additional data flow and, in turn, causing increased internal queuing. Staging too much data also means that more cache memory is used than is necessary which lowers the hit rate because other, likely to be referenced data must be removed from the cache memory to make room for the excess data being staged in the cache memory.
Conversely, staging too little data results in higher miss rate because records that should have been in cache memory are not there. A higher miss rate leads to a higher response time thus lower computer system operations efficiency which is manifested by excessive system resources use through increased rate of disk seeks and busy data paths. To mitigate this problem, modern controllers employ methods which facilitate a more flexible approach to data storage.
For example, Hitachi Data Systems (HDS) cache control subsystems model numbers HDS 7700 and HDS 7750 utilize three algorithms to manage cache memory usage: a Sequential Prefetch algorithm, a Least Recently Used (LRU) algorithm, and an Intelligent Learning algorithm. The Sequential Prefetch algorithm, enables prefetching of at least one full set of tracks to satisfy subsequent access from cache at host data transfer speeds. The LRU algorithm, controls the allocation of cache memory segments by placing LRU segments in an LRU list. The Intelligent Learning algorithm, maximizes cache memory usage by identifying random and sequential data access patterns and selecting the amount of data to be staged in cache-- that is, a record, a partial track, or a full track. However, it does not appear that this combination of algorithms selects the optimal amount of data to stage.
Other modern controllers, used for example in IBM 3990, also facilitate a more flexible approach to data storage for mitigating the problem of choosing the wrong amount of data to stage. Such controllers employ algorithms that allow caching, or more precisely staging, in one of two modes: record staging, and staging to the end of track. Whereas, record staging is storage in cache memory of a requested record alone, staging to the end of track is storage in cache memory of all records starting from the originally requested record to the end of the track. However, such controllers include arbitrary or empirical decision factors (commonly called "fudge factors") in determining which of the staging modes will produce better performance which, in fact, is not necessarily the optimal performance.
Accordingly, what is needed is a method and a system for optimizing the management of data caching. A method and system for optimizing the management of data caching need to, reliably and consistently, optimize utilization of computer system resources. Such a method and system need also to improve the hit rate. The present invention provides such a method and a system.